EFI MCU Resource Allocation

Copyright © 2000 Bernd Felsche , Perth, Western Australia.
This page describes the allocation of MCU resources to external and internal functions.

The resources available are based on the Atmel 8535 MCU. This chip is an 8-bit RISC MPU with 8-channel ADC, 32 digital I/O, RTC capability, UART, 2x8-bit timer/counters, one 16-bit timer/counter, a watchdog counter, in-built PWM on the 16-bit and one of the 8-bit counters. There's 8K bytes of flash for program memory, 512 bytes of EEPROM and 512 bytes of SRAM. Flash and EEPROM are in-system-programmable via a slave processor interface (SPI). Various power-saving modes are supported; keeping SRAM alive with only a few micro-amps.

Required base functionality is defined by existing Digifant II architecture. The Digifant architecture utilises much of the L-Jetronic hardware such as air-flow meter, air and coolant temperature sensors, O2 sensor (except those without a cat-convertor never had it), an idle-stabiliser valve to bypass air past the throttle and of course pulsed injectors, all wired as one group. Timing is based on a Hall-sensor in a static distributor, providing only timing pulses at 6° and 78° before TDC. A knock sensor is also used by Digifant.

Pin Allocation|Timers/Counters| Interrupts
Pin Allocation
Pin NameDefinitionDirAllocation
VCCDigital supply voltage NRegulated Power
GNDDigital ground NRegulated power rail ground
PA0
ADC0
Analog in; Digital In/Out I Air flow
PA1
ADC1
Analog in; Digital In/Out I Air temp
PA2
ADC2
Analog in; Digital In/Out I Coolant temp
PA3
ADC3
Analog in; Digital In/Out I Battery volts
PA4
ADC4
Analog in; Digital In/Out I Knock Detection
PA5
ADC5
Analog in; Digital In/Out I O2 Sensor
PA6
ADC6
Analog in; Digital In/Out -  
PA7
ADC7
Analog in; Digital In/Out -  
PB0
T0
Digital In/Out I Hall Sensor 6/78° BTDC
Same as PD6 == ICP
PB1
T1
Digital In/Out -  
PB2
AIN0
Digital In/Out I Backup battery voltage
PB3
AIN1
Digital In/Out I Backup battery ref level
PB4
SS
Digital In/Out N Communications Bus
PB5
MOSI
Digital In/Out N Communications Bus
PB6
MISO
Digital In/Out N Communications Bus
PB7
SCK
Digital In/Out N Communications Bus
PC0Digital In/Out I WOT/Idle switches (common)
PC1Digital In/Out I Starter turning
PC2Digital In/Out I Airconditioner running
PC3Digital In/Out O Fuel pump relay
PC4Digital In/Out O Head-unit (chip) select
PC5Digital In/Out O Knock chip select
PC6
TOSC1
Digital In/Out IO Knock chip integration start/finish
PC7
TOSC2
Digital In/Out -  
PD0
RXD
Digital In/Out I Serial port RXD
PD1
TXD
Digital In/Out O Serial port TXD
PD2
INT0
Digital In/Out -  
PD3
INT1
Digital In/Out I Restart interrupt to wake from SLEEP
PD4
OC1B
Digital In/Out O Fuel Injector Group 0
PD5
OC1A
Digital In/Out I Ignition
PD6
ICP
Digital In/Out I Hall Sensor in distributor
6 and 78° BTDC
PD7
OC2
Digital In/Out O Idle Stabiliser Valve
RESETReset input. Low for two cycles resets device N As per data sheet
XTAL1Input to inverting osc. amp and internal clock N for 8 MHz
XTAL2Output from inverting osc. amp N for 8 MHz
AVCCSupply for ADC N VCC with low-pass filtering
AREFReference voltage for ADC N Regulated ref - 3V
AGNDAnalog ground. N Shielded ground common for analog signals
Pin Allocation|Timers/Counters| Interrupts
Copyright © 2000 Bernd Felsche , Perth, Western Australia.

Timers/Counters
TimerResolutionClock Rate Allocation
TC08-bitT0 Half-Rev Counter. Used for
  • Knock management,
  • Speed change response monitoring,
  • Engine revolutions counter via interrupt handling on overflow,
  • others...
TC116-bitCK/64 Engine Base Timing - All the operations for injection and ignition have their timing based on this counter.
  • ICP (input capture) used to determine engine "TDC" and "BDC" positions via an interrupt routine. The Hall sensor provides signals at nominally 6° and 78° BTDC with negative- and positive- going signals so it's easy to discern which is which. It's possible to use only one edge at higher engine speeds and to use both at lower engine speeds, especially to maintain idle stability under load.
    Engine RPM Count Crank Resolution
    20018 750 0.0096°
    6000625 0.288°
    Timing resolution is constant at 64/8MHz = 8µs
    NB: Use of a different pre-scaler (of 8, the next available) would result in overflows at cranking speeds.
  • OCR1A used for FI start and end. Also schedules house-keeping (e.g. scanning analog conversions, determining new operational values, feeding the watchdog) either during or after injection.
  • OCR1B used for ignition coil charge and spark (dwell and trigger), knock-chip start-of-integration signal and knock evaluation start.
  • Interrupts on compare match for OCR1A and OCR1B to set the next event count. The compare register operational state is maintained separately so that the functionality of each can be overloaded.
  • Interrupts on overflow are used to determine the operation of the fuel pump.
TC28-bitTCK2/1024 PWM used for idle stabiliser
  • OCR2 used to set duty cycle
  • PD7 is output
Watchdog16 to 2048ms1MHz 256K cycles (approx 256ms) used as pre-scaler to avoid handling more than one watchdog interrupt per half-crank when starting. It may be desirable to decrease the prescale to something like 64K cycles (depending on idle speed) once the engine is idling.
Pin Allocation|Timers/Counters| Interrupts
Copyright © 2000 Bernd Felsche , Perth, Western Australia.

Interrupts
VectorSourceDefinition Allocation
1RESETPin and Watchdog Reset  
2INT0External Interrupt Request 0  
3INT1External Interrupt Request 1 Low-power save and sleep / power-on restart
4TIMER2 COMP Timer/Counter 2 compare match not used - PWM
5TIMER2 OVF Timer/Counter 2 overflow not used - PWM
6TIMER1 CAPT Timer/Counter 1 capture event TDC/BDC marker
7TIMER1 COMPA Timer/Counter 1 compare match A Fuel injection timing and housekeeping
8TIMER1 COMPB Timer/Counter 1 compare match B Ignition dwell/timing and knock sense integration trigger
9TIMER1 OVFTimer/Counter 1 overflow Fuel pump control
10TIMER0 OVF Timer/Counter 0 overflow Engine revolutions counter
11SPI, STCSerial transfer complete Host bus transmissions; in-system-programming
12UART, RXUART Rx complete Raw diagnostic
13UART, UDREUART Data register empty Raw diagnostic
14UART, TXUART Tx complete Raw diagnostic
15ADCADC Complete Conversions of quantities
16EE_RDYEEPROM Ready Save adapted/trimmed parameters
17ANA_COMPAnalog comparator Power-off
Pin Allocation|Timers/Counters| Interrupts
Copyright © 2000 Bernd Felsche , Perth, Western Australia.